1. Field of the Invention
Generally, the present disclosure generally relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to a method forming conductive contacts on semiconductor devices that include two or more stress liners for inducing desired stresses in the channel regions of the devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a large number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors (NMOS) and/or P-channel transistors (PMOS), are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions.
In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends upon a variety of factors, such as the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length.
There is a constant and continuous drive to increase the performance of NMOS and PMOS transistor devices. One technique for improve such performance is to reduce the channel length of the transistor device. For example, the gate length of such transistors has been dramatically reduced in the past 20 years to improve the switching speed and drive current capability of such devices. The progress has been such that current day transistor devices have gate lengths of approximately 0.3-0.8 μm and further reductions are anticipated in the future. Another technique used to increase the performance of transistor devices has been to incorporate more sophisticated materials into such devices, e.g., the use of metal gate electrodes, the use of so-called high-k dielectric materials (k value greater than 10) and the use of copper based metallization layers.
Another technique used to improve device performance is related to establishing certain stresses in the channel region of the transistors. This is typically accomplished by forming one or more layers of material, such as silicon nitride, above the transistor that imparts or induces the desired stress in the channel region of the device. In general, it is desirable to create a tensile stress in the channel region of NMOS transistors to increase their performance. In contrast, it is desirable to create a compressive stress in the channel region of the PMOS transistors. The techniques employed in forming such stress inducing layers for selective channel stress engineering purposes are well known to those skilled in the art.
One illustrative prior art technique for forming such stress inducing layers will now be described with reference to FIGS. 1A-1D. FIG. 1A is a simplified view of an illustrative semiconductor device 100 at an early stage of manufacturing that is formed above a semiconducting substrate 10. The device generally comprised an illustrative PMOS transistor 100P and an illustrative NMOS transistor 100N formed in an PMOS region 10P and an NMOS region 10N, respectively, of the substrate 10. At the point of fabrication depicted in FIG. 1A, each of the PMOS transistor 100P and the 1MOS transistor 100N includes a gate electrode structure that includes an illustrative gate insulation layer 20 that may be made of, for example, silicon dioxide, and an illustrative gate electrode 22 that may be made of, for example, polysilicon. Each of the illustrative devices 100P, 100N, depicted in FIG. 1A also includes illustrative sidewall spacers 24, source/drain regions 26, metal silicide regions 28 and isolation regions 12. The configuration and composition of these structures may also vary depending upon the application, and they may be manufactured using techniques well known to those skilled in the art. The gate electrode 22, the gate insulation layer 20, the sidewall spacers 24, the source/drain regions 26, the metal silicide regions 28 and the isolation regions 12 may be manufactured using techniques known to those skilled in the art.
The prior art process begins with the formation of a so-called stop oxide stop layer 29, e.g., silicon dioxide, above the gate electrode structures of both the PMOS device 100P and the NMOS device 100N and the substrate 10. Thereafter, a first stress inducing layer 30T. e.g., silicon nitride, is formed above the etch stop layer 29 in both the PMOS and NMOS regions 10P, 10N of the device 100. The first stress inducing layer 30T is manufactured or treated such that it will impart the desired tensile stress in the channel region of the NMOS transistor 100N. Still referring to FIG. 1A, the next step involves formation of a so-called end point oxide 32, e.g., silicon dioxide, in the PMOS region 10P and NMOS region 10N above the first stress inducing layer 30T. Then, a mask layer 34, e.g., a photoresist mask, is formed to protect the NMOS device 100N while exposing the PMOS device 100P to further processing.
Next, as shown in FIG. 1B, one or more etching process are performed to remove the end point oxide 32 and the first stress inducing layer 30T from above the PMOS region 10P. During this etching process used to remove the first stress inducing layer 30T, the etch stop layer 29 is subject to attack and erosion due to the poor etch selectivity of the etching process used to remove the first stress inducing layer 30T, e.g., silicon nitride, relative to the etch stop oxide 29, e.g., silicon dioxide. In some cases, at least portions of the etch stop layer 29 in the PMOS region 10P may be degraded to the point where at least some of the underlying metal silicide regions 28, e.g., nickel silicide, may be exposed, or the thickness of the etch stop layer 29 may be reduced such that it is no longer effective in protecting the underlying metal silicide regions 28. This degradation of the etch stop oxide 29 is schematically reflected in the reduced thickness of the etch stop oxide 29 in the PMOS region 10P of the device. In some cases, the etch stop oxide 29 is so degraded that damage to the underlying metal silicide regions 28 may occur at this point during the fabrication process. Another potential problem with the degradation of the etch stop layer 29 is that it may be so degraded in the etching process performed to remove the first stress inducing layer 30T in the PMOS region 10P that the silicon nitride spacers 24 may also be attacked during the etching process, which has the potential for weakening or eliminating the protection, i.e., nitride encapsulation, provided for the gate structure.
Next, as shown in FIG. 1C, a second stress inducing layer 30C, e.g., silicon nitride, is formed above the PMOS region 10P and NMOS region 10N of the device 100. Note that the second stress inducing layer 30C is formed above the degrade etch stop layer 29 in the PMOS region 10P. The second stress inducing layer 30C is manufactured or treated such that it will impart the desired compressive stress in the channel region of the PMOS transistor 100P. A mask layer 38, e.g., a photoresist mask, is then formed to protect the PMOS device 100P while exposing the NMOS device 100N to further processing.
Next, as shown in FIG. 1D, one or more etching process are performed to remove the second stress inducing layer 30C from above the NMOS region 10N while stopping on the end point oxide 32 in the NMOS region 100N. Typically, the end point oxide 32 is not removed in the NMOS region 10N. Rather, processing operations are commenced form conductive contacts to the source/drain regions 26 and the gate electrodes 22 of the NMOS device 10N and PMOS device 10P. This typically involves the formation of one or more layers of insulating materials (not shown) above the device 100, and thereafter forming openings in the layer of insulating material where conductive contact will be formed.
As mentioned above, one significant problem with this illustrative prior art technique is the resulting degraded etch stop layer 29 in the PMOS region 10P of the device 100. During the contact formation process an etching process will be performed to form an opening through the second stress inducing layer 30C so that a contact can eventually be made to the underlying source/drain regions 26. In theory, the etch stop layer 29 is supposed to stop the etching process performed to form the opening through the second stress inducing layer 30C. However, due to the aforementioned degradation of the etch stop layer 29 in the PMOS region 10P, the metal silicide regions 28 may be attacked and at least partially destroyed during this etching process, thereby undesirably at least increasing the resistance of the contact to be formed for the source/drain region. Such processing errors can result in the production of devices that exhibit poor or reduced performance capability, and in a worst case, devices that simply do not work.
The present disclosure is directed to various methods and resulting devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.